1. Field of the Invention
The present invention relates to a digital signal processor and particularly to a digital signal processor improved so that digital signal processing can be performed efficiently.
2. Description of the Prior Art
A digital signal processor is a microprocessor dedicated to digital signal processing, developed for the purpose of rapidly performing multiplication and addition operations frequently required for digital signal processing.
FIG. 1 is a schematic block diagram showing an example of a conventional digital signal processor disclosed for example in "A Single-Chip Digital Signal Processor for Voiceband Applications" by Y. Kawakami et al, 1980 IEEE International Solid-State Circuits Conference, pp. 40-41. Referring to FIG. 1, this conventional digital signal processor comprises, as in an ordinary microcomputer, a memory portion 1, a control portion 2, an arithmetic operation portion 3 and a data bus 4. The memory portion 1 comprises a random access memory (referred to hereinafter as a RAM) 11 and a read only memory (referred to hereinafter as a ROM) 12. Data to be processed in the arithmetic operation portion 3 and data necessary for this processing are stored in the RAM 11 and the ROM 12. Non fixed data is stored in the RAM 11 and fixed data (such as constant data for multiplication) is stored in the ROM 12. The RAM 11 and the ROM 12 are connected with the data bus 4.
The control portion 2 comprises an instruction ROM 21, a program counter 22, an instruction resistor 23 and an instruction decoder 24. Program data is stored in the instruction ROM 21. The program counter 22 reads out successively program data from the instruction ROM 21 in synchronism with a basic clock (not shown) of the digital signal processor. The instruction resistor 23 stores temporarily the program data read out from the instruction ROM 21. An output from the instruction resistor 23 is supplied to the instruction decoder 24. Part of bit output from the instruction resistor 23 is supplied to the data bus 4. The instruction decoder 24 decodes the program data received from the instruction resistor 23 and provides various control signals. Those control signals are supplied to the memory portion 1, the control portion 2, the arithmetic operation portion 3 etc. so as to control the operation of the internal circuits of those components.
The calculating portion 3 comprises a multiplier 31, an arithmetic and logic unit (referred to hereinafter as an ALU) 32 and an accumulator 33. Inputs of the multiplier 31 are connected with the data bus 4. One of the inputs of the multiplier 31 is connected directly with the RAM 11 and the other input thereof is connected directly with the ROM 12. An input of the ALU 32 is connected with the data bus 4 and is also connected directly with the multiplier 31. The other input of the ALU 32 receives an output from the accumulator 33. An output from the ALU 32 is supplied to the accumulator 33. The accumulator 33 is connected with the data bus 4.
In the above described construction, the multiplier 31 multiplies a value read out from the RAM 11 by a constant read out from the ROM 12 and supplies the result to the ALU 32. The ALU 32 adds the result of multiplication by the multiplier 31 to the accumulating total value of the results of multiplications performed so far and stored in the accumulator 33 and stores the result of addition in the accumulator 33. The accumulating total value stored in the accumulator 33 is provided through the data bus 4.
Since the digital signal processor comprises the multiplier 31 as a hardware circuit dedicated to multiplication processing as described above, multiplication processing can be performed at a higher speed compared with the case in which multiplication is performed in the ALU 32 as repetition of addition as in a conventional microcomputer. In addition, since the multiplier 31 is connected directly with the RAM 11 and the ROM 12, data can be set in the multiplier 31 by one instruction. Furthermore, since the multiplier 31 is connected directly with the ALU 32, a result of multiplication can be set in the ALU 3 by one instruction. Thus, the data paths for multiplication and addition operations are provided separately from the data bus 4 and accordingly multiplication and addition operations and transfer of data can be performed simultaneously and processing for multiplication and addition operations can be performed at high speed.
In such a conventional digital signal processor as described above, data to be multiplied is stored in the RAM 11 and as a result there is involved a problem that several instructions are required for execution of processing to delay the data (such processing is often required in a digital filter or the like). For example, with regard to the processing for delaying data for one sample, the following instructions are required.
(1) To set an address n in the RAM 11.
(2) To store the content of the address n in the RAM 11 into a first temporary resistor (not shown) and at the same time to increment the address in the RAM 11.
(3) To store the content of the address (n+1) in the RAM 11 into a second temporary resistor (not shown).
(4) To write the content of the first temporary resistor into the address (n+1) in the RAM 11.
As described above, it is necessary in the conventional digital signal processor to save temporarily in the temporary resistor the data stored in the RAM 11 and to write again in the RAM 11 the data saved in the temporary resistor after having incremented the address in the RAM 11. Consequently, in order to make delay for one sample, several instructions are required. Moreover, it is necessary to perform the above described processing for all the data to be delayed for one sample.